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| SPICE Device Model SUM60N10-17 Vishay Siliconix N-Channel 100-V (D-S) 175C MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72140 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM60N10-17 Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 3.2 366 0.013 0.015 0.024 0.030 0.90 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = 250 A VDS 5 V, VGS = 10 V VGS = 10 V, ID = 30 A V A 0.013 0.015 Drain-Source On-State Resistancea rDS(on) VGS = 6 V, ID = 20 A VGS = 10 V, ID = 30 A, TJ = 125C VGS = 10 V, ID = 30 A, TJ = 175C Forward Voltage a VSD IF = 30 A, VGS = 0 V 1 V Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Chargec Gate-Drain Charge c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr IF = 50 A, di/dt = 100 A/s VDD = 50 V, RL = 1.5 ID 60 A, VGEN = 10 V, RG = 2.5 VDS = 50 V, VGS = 10 V, ID = 60 A VGS = 0 V, VDS = 25 V, f = 1 MHz 4377 482 239 57 25 19 25 12 17 10 110 4300 450 175 65 25 19 15 12 30 10 125 ns nC pF Turn-On Delay Timec Rise Timec Turn-Off Delay Timec Fall Timec Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 72140 09-Jun-04 SPICE Device Model SUM60N10-17 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 72140 09-Jun-04 www.vishay.com 3 |
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